`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    08:37:33 04/20/2011 
// Design Name: 
// Module Name:    Mux_2to1_4bits 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_2to1_4bits(a, b, sel, out);
   input [3:0] a;
   input [3:0] b;
   input sel;
   output [3:0] out;

	reg [3:0] out;
	
	always @ (*)
	begin
		if (sel == 0)
			out <= a;
		else
			out <= b;
	end
	
endmodule
